Linear regression is one of the most widely used statistical methods available today. It is used by data analysts and students in almost every discipline. However, for the standard ordinary least squares method, there are several strong assumptions made about data that is often not true in real world data sets. This can cause numerous problems in the least squares model. One of the most common issues is a model overfitting the data. Ridge Regression and LASSO are two methods used to create a better and more accurate model. I will discuss how overfitting arises in least squares models and the reasoning for using Ridge Regression and LASSO include analysis of real world example data and compare these methods with OLS and each other to further infer the benefits and drawbacks of each method.
This is the template for DAM (discrete and argumentative mathematics).
We prove theorem $2.1$ using the method of proof by way of contradiction. This theorem states that for any set $A$, that in fact the empty set is a subset of $A$, that is $\emptyset \subset A$.
In this paper I demonstrate a novel design for an optoelectronic State Machine which replaces input/output forming logic found in conventional state machines with BDD based optical logic while still using solid state memory in the form of flip-flops in order to store states. This type of logic makes use of waveguides and ring resonators to create binary switches. These switches in turn can be used to create combinational logic which can be used as input/output forming logic for a state machine. Replacing conventional combinational logic with BDD based optical logic allows for a faster range of state machines that can certainly outperform conventional state machines as propagation delays within the logic described are in the order of picoseconds as opposed to nanoseconds in digital logic.
Este esquema representa un circuito integrado de tecnología CMOS 74VHC153 que representa dos multiplexores con las siguientes características:
Dos entradas de habilitación de cada mitad, denominadas Ea y Eb
Dos entradas de direccionamiento comunes Sa y Sb
Dos salidas (1 por cada multiplexor)
Cuatro entradas de datos (Ina e Inb) por cada multiplexor
Este esquema ha sido tomado y adaptado de la hoja de especificaciones loclizada en http://www.fairchildsemi.com/datasheets/74/74VHC153.pdf